The Dual-Use and Related Goods (Export Control) Regulations 1995

A

Chemical Vapour Deposition (CVD)

B

Thermal-Evaporation Physical Vapour Deposition (TE-PVD)

1

Physical Vapour Deposition (PVD): Electron-Beam (EB-PVD)

B.2

Ion assisted resistive heating Physical Vapour Deposition (Ion Plating

B.3

Physical Vapour Deposition: “laser”evaporation

B.4

Physical Vapour Deposition: cathodic arc discharge

C

Pack cementation (see A above for out-of-pack cementation) (10)

D

Plasma spraying

E

Slurry Deposition

F

Sputter Deposition

G

Ion Implantation

Outline of the CTP calculation method

CTP is a measure of computational performance given in Mtops. In calculating the CTP of an aggregation of CEs the following three steps are required:

1

Calculate the effective calculating rate R for each CE;

2

Apply the word length adjustment (L) to the effective calculating rate (R), resulting in a Theoretical Performance (TP) for each CE;

3

If there is more than one CE, combine the TPs resulting in a CTP for the aggregation.

Note W:

For a pipelined CE capable of executing up to one arithmetic or logic operation every clock cycle after the pipeline is full, a pipelined rate can be established. The effective calculating rate (R) for such a CE is the faster of the pipelined rate or non-pipelined execution rate.

Note X:

For CEs which perform multiple operations of a specific type in a single cycle (e.g., two additions per cycle or two identical logic operations per cycle), the execution time t is given by:

$t=cycle timethe number of identical arithmetic operations per machine cycle$

CEs which perform different types of arithmetic or logic operations in a single machine cycle are to be treated as multiple separate CEs performing simultaneously (e.g., a CE performing an addition and a multiplication in one cycle is to be treated as two CEs, the first performing an addition in one cycle and the second performing a multiplication in one cycle).

If a single CE has both scalar function and vector function, use the shorter execution time value.

Note Y:

For the CE that does not implement FP add or FP multiply, but that performs FP divide:

$Rfp=1tfpdivide$

Note Z:

In simple logic operations, a single instruction performs a single logic manipulation of no more than two operands of given lengths. In complex logic operations, a single instruction performs multiple logic manipulations to produce one or more results from two or more operands.

• Rates should be calculated for all supported operand lengths considering both pipelined operations (if supported), and non-pipelined operations using the fastest executing instruction for each operand length based on: Pipelined or register-to-register operations. Exclude extraordinarily short execution times generated for operations on a predetermined operand or operands (for example, multiplication by 0 or 1). If no register-to-register operations are implemented, continue with (2). The faster of register-to-memory or memory-to-register operations; if these also do not exist, then continue with (3). Memory-to-memory.

• In each case above, use the shortest execution time certified by the manufacturer.

This adjustment is not applied to specialized logic processors which do not use XOR instructions. In this case TP = R.

Select the maximum resulting value of TP for:

• Each XP-only CE (Rxp);

• Each FP-only CE (Rfp);

• Each combined FP and XP CE (R);

• Each simple logic processor not implementing any of the specified arithmetic operations; and

• Each special logic processor not using any of the specified arithmetic or logic operations.

Step 3: CTP for aggregations of CEs, including CPUs

For a CPU with a single CE,

$CTP=TP$

(for CEs performing both fixed and floating point operations

$TP=max ( TP fp, TP xp )$

)

CTP for aggregations of multiple CEs operating simultaneously is calculated as follows:

Note 1:

For aggregations that do not allow all of the CEs to run simultaneously, the possible combination of CEs that provides the largest CTP should be used. The TP of each contributing CE is to be calculated at its maximum value theoretically possible before the CTP of the combination is derived.

• N.B. To determine the possible combinations of simultaneously operating CEs, generate an instruction sequence that initiates operations in multiple CEs, beginning with the slowest CE (the one needing the largest number of cycles to complete its operation) and ending with the fastest CE. At each cycle of the sequence, the combination of CEs that are in operation during that cycle is a possible combination. The instruction sequence must take into account all hardware and/or architectural constraints on overlapping operations.

Note 2:

A single integrated circuit chip or board assembly may contain multiple CEs.

Note 3: